1. Field of the Invention
The present invention relates to a clock recovery circuit and, more particularly, to a clock recovery circuit to be used for high-speed data signal transmission.
2. Description of the Related Art
Recently, the performance of components used in computers and other information processing apparatuses has been greatly improved. In particular, dramatic improvements have been made, for example, in the performance of semiconductor memory devices such as SRAMs (Static Random Access Memories) and DRAMs (Dynamic Random Access Memories), and other semiconductor devices such as processors and switching LSIs.
The improvements in the performance of semiconductor memory devices, processors, and the like have reached the point where system performance cannot be improved further unless the speed of signal transmission between components or elements is increased. Specifically, the speed gap between a DRAM and a processor (i.e., between LSIs), for example, has been widening year by year, and in recent years, this speed gap has been becoming a bottleneck impeding performance improvement for a computer as a whole. Furthermore, with increasing integration and increasing size of semiconductor chips, the speed of signal transmission between elements or circuit blocks within a chip is becoming a major factor limiting the performance of the chip. Moreover, the speed of signal transmission between a peripheral device and the processor/chipset is also becoming a factor limiting the overall performance of the system.
Generally, in high-speed signal transmission between circuit blocks or chips or between cabinets, a clock used to discriminate between data “0” and data “1” is generated (recovered) using a clock recovery circuit at the receiving end. The recovered clock is phase-adjusted by a phase adjusting circuit in the clock recovery circuit so that the clock has a constant phase relationship with respect to the received signal in order to ensure correct signal reception at all times. The process of recovering the clock and discriminating the data using the thus recovered clock is called the CDR (Clock and Data Recovery); here, to achieve high-speed signal transmission, for example, the duty cycle of the recovered clock must be controlled accurately. Therefore, it is strongly demanded to provide a clock recovery circuit capable of maintaining the duty cycle of the recovered clock at a prescribed value.
The prior art and its associated problem will be described in detail later with reference to relevant drawings.